Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores

Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Dan Zhao, Unni Chandran, Hideo Fujiwara
• Keywords: ASPDAC 2007, Certain Virtual Cores, Hardware, Multifrequency Wrapper Architecture, Wrapper Architecture