Simplifying Instruction Issue Logic in Superscalar Processors

Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is dicult to increase the size without anyseriousimpactonprocessorperformance,sincetheinstruction windowisoneofthedominantdeterminersofprocessorcycletime. The instruction window is critical because it is realized using content addressable memory (CAM). In general, RAMs are faster in accesstime and lower inpowerdissipationthan CAMs. Therefore, it is desirable that the CAM instruction window is replaced by the RAMinstructionwindow. Thispaperproposessuchaninstruction window, named the explicit data forwarding instruction window. The principle behind our proposal is to make result forwarding explicit. It is possible to dynamically construct explicit relationships between instructions, since it is expected that each execution result is forwarded to a limited number of dep...

• Type: Conference
• Year: 2002
• Where: DSD
• Authors: Toshinori Sato, Itsujiro Arita
• Keywords: Data Forwarding Instruction, DSD 2002, Hardware, Instruction, Instruction Window