ERSA
2009
13 years 9 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
CASES
2010
ACM
13 years 9 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
TVLSI
2002
13 years 11 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
TCAD
2002
13 years 11 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
CE
2005
13 years 11 months ago
2005
The current study examined the effects of non-interactive computer assisted instruction on students
IJLT
2007
13 years 11 months ago
2007
: Differentiated instruction is an approach to teaching that acknowledges people have multiple paths for learning and for making sense of ideas. In e-learning, differentiated instr...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
JCP
2008
13 years 11 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
CJ
2006
13 years 11 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...