Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures

In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
• Keywords: Bus Frequency Assignment, Bus Partitioning, DATE 2005, Hardware, Power Consumption