Slice-processors: an implementation of operation-based prediction

We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operations, or the computation slice that can be used to calculate forthcoming memory references. This is in contrast to outcome-based predictors that exploit regularities in the (address) outcome stream. Slice processors are a generalization of existing operation-based prefetching mechanisms such as stream buffers where the operation itself is fixed in the design (e.g., address + stride). A slice processor dynamically identifies frequently missing loads and extracts on-the-fly the relevant address computation slices. Such slices are then executed in-parallel with the main sequential thread prefetching memory data. We describe the various support structures and emphasize the design of the slice detection mechanism. We demonstrate that a slice processor can significantly improve performance over an aggressive, dynamica...

• Type: Conference
• Year: 2001
• Where: ICS
• Authors: Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
• Keywords: Computation Slices, Distributed And Parallel Computing, ICS 2001, Slice Processor, Slice Processor Micro-architecture