ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache missrate of a multiprocessing system with any cache size and t...
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
ËØ Ø Ó Ø ÖØ Â Ú Î ÖØÙ Ð Å Ò × Û Ø ÂÙ×عÁÒ¹Ì Ñ ´ÂÁ̵ ÓÑÔ Ð Ö× Ñ Ù× Ó Ú Ò ÓÑÔ Ð Ö Ø Ò Õ٠׸ ÖÙÒ¹Ø Ñ ÔÖÓ¬Ð Ò Ò ...
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
106
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ICS
2001
Tsinghua U.
14 years 3 months ago
2001
Tsinghua U.
For most parallel and high performance systems, tuning guides provide the users with advices to optimize the execution time of their programs. Execution time may be very sensitive...