Software Decelerators

This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed penalty in order to derive overall system benefits in terms of improved resource use (e.g. reduced area or lower power consumption) and/or a more efficient design process. The background rationale for such a strategy is the increasing availability of embedded processors ‘for free’ in Platform FPGAs. A detailed case study of the concept is presented, involving the provision of a high-level technology-independent design methodology based upon a finite state machine model. This illustrates easier design and saving of logic resource, with timing performance still meeting necessary requirements.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: Eric Keller, Gordon J. Brebner, Philip James-Roxby
• Keywords: Efficient Design Process, FPL 2003, Lower Power Consumption, Speed Penalty