Solver technology for system-level to RTL equivalence checking

—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, whereas the RTL implementation is created by a hardware designer. This approach leads to two models that are significantly different. Checking the equivalence of real-life designs requires strong solver technology. The challenges can only be overcome with a combination of bit-level and word-level reasoning techniques, combined with the right orchestration. In this paper, we discuss solver technology that has shown to be effective on many real-life equivalence checking problems.

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley
• Keywords: DATE 2009, Hardware, Real-life Equivalence Checking, Solver Technology, System-level Model