Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic

This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Arrays (FPGAs). This approach has become feasible due to recent advances in Reconfigurable Computing. We develop an algorithm that is suitable for a logic circuit implementation. This algorithm is basically equivalent to the Davis-Putnam procedure with Experimental Unit Propagation. The required hardware resources for the algorithm are less than those of MOM's heuristics.

• Type: Conference
• Year: 1999
• Where: IPPS
• Authors: Takayuki Suyama, Makoto Yokoo, Akira Nagoya
• Keywords: Algorithm, Distributed And Parallel Computing, IPPS 1999, Logic Circuit, Programmable Gate Arrays