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CORR
2008
Springer
142views Education» more  CORR 2008»
14 years 15 days ago
Declarative Combinatorics: Boolean Functions, Circuit Synthesis and BDDs in Haskell
We describe Haskell implementations of interesting combinatorial generation algorithms with focus on boolean functions and logic circuit representations. First, a complete exact c...
Paul Tarau
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
14 years 4 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
14 years 4 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
IPPS
1999
IEEE
14 years 4 months ago
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field ...
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
ISMVL
2008
IEEE
148views Hardware» more  ISMVL 2008»
14 years 6 months ago
Quantum Logic Implementation of Unary Arithmetic Operations
The mathematical property of inheritance for certain unary fixed point operations has recently been exploited to enable the efficient formulation of arithmetic algorithms and circ...
Mitchell A. Thornton, David W. Matula, Laura Spenn...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 7 months ago
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuy...
DATE
2009
IEEE
103views Hardware» more  DATE 2009»
14 years 7 months ago
Masking timing errors on speed-paths in logic circuits
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
Mihir R. Choudhury, Kartik Mohanram