Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture

— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors— which results in smaller area, higher speeds, and lower energy dissipation. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with Split-Row decoding is within 0.3–0.6 dB of the Min-Sum and Sum-Product decoding algorithms. A full parallel decoder for a (3,6) LDPC code with a code length of 1536 bits is implemented in a 0.18 µm CMOS technology twice: once using the Split-Row method, and once using the Min-Sum algorithm for comparison. The Split-Row decoder operates at 53 MHz and delivers a throughput of 5.4 Gbps with 15 decoding iterations per

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Tinoosh Mohsenin, Bevan M. Baas
• Keywords: Hardware, ICCD 2006, LDPC Decoding Method, Row Processor Parallelism, Sum-Product Decoding Algorithms