ICCD 2006 - PDF Preprint Papers

ICCD 2006 International Conference on Computer Design

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ICCD
2006
IEEE

312views Hardware» more ICCD 2006»

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals

14 years 8 months ago

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— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...

Kimiyoshi Usami, Naoaki Ohkubo

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Id	Views	Title	Status

1	312	A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals	claim
2	275	Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture	claim
3	189	A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems	claim
4	185	An accurate Energy estimation framework for VLIW Processor Cores	claim
5	183	An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks	claim
6	182	A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips	claim
7	171	Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach	claim
8	166	FPGA Implementation of High Speed FIR Filters Using Add and Shift Method	claim
9	157	Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation	claim
10	157	Dynamic Co-Processor Architecture for Software Acceleration on CSoCs	claim
11	148	Trends and Future Directions in Nano Structure Based Computing and Fabrication	claim
12	143	Improving Power and Data Efficiency with Threaded Memory Modules	claim
13	140	Clustering-Based Microcode Compression	claim
14	139	Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors	claim
15	138	Design and Implementation of Software Objects in Hardware	claim
16	138	Delay and Area Efficient First-level Cache Soft Error Detection and Correction	claim
17	137	Implementation and Evaluation of On-Chip Network Architectures	claim
18	137	Reduction of Crosstalk Pessimism using Tendency Graph Approach	claim
19	134	Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD	claim
20	133	Patching Processor Design Errors	claim
21	132	FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems	claim
22	131	Power-Constrained SOC Test Schedules through Utilization of Functional Buses	claim
23	128	Polaris: A System-Level Roadmap for On-Chip Interconnection Networks	claim
24	127	CMOS Comparators for High-Speed and Low-Power Applications	claim
25	127	Power Droop Testing	claim
26	126	Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems	claim
27	125	Partial Functional Manipulation Based Wirelength Minimization	claim
28	124	Customizable Fault Tolerant Caches for Embedded Processors	claim
29	123	Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug	claim
30	123	Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates	claim
31	121	A Low Power Highly Associative Cache for Embedded Systems	claim
32	121	Power/ground supply network optimization for power-gating	claim
33	119	FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling	claim
34	118	A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models	claim
35	117	System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors	claim
36	117	Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses	claim
37	116	RTL Scan Design for Skewed-Load At-speed Test under Power Constraints	claim
38	115	Long-term Performance Bottleneck Analysis and Prediction	claim
39	115	Microarchitecture and Performance Analysis of Godson-2 SMT Processor	claim
40	113	High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding	claim
41	113	A theory of Error-Rate Testing	claim
42	113	Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache	claim
43	111	Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique	claim
44	109	Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling	claim
45	109	Scaling Manufacturability Software to Thousands of Processors	claim
46	107	Design and Implementation of the TRIPS Primary Memory System	claim
47	105	A New Class of Sequential Circuits with Acyclic Test Generation Complexity	claim
48	104	Guiding Architectural SRAM Models	claim
49	103	Architectural Support for Run-Time Validation of Control Flow Transfer	claim
50	103	Requirements and Concepts for Transaction Level Assertions	claim
51	103	Reduce Register Files Leakage Through Discharging Cells	claim
52	101	A Pattern Generation Technique for Maximizing Power Supply Currents	claim
53	99	High-Level vs. RTL Combinational Equivalence: An Introduction	claim
54	97	Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection	claim
55	96	An Efficient, Scalable Hardware Engine for Boolean SATisfiability	claim
56	96	Synthesis of Regular Logic Bricks for Robust IC Design	claim
57	96	An Enhancement for a Scheduling Logic Pipelined over two Cycles	claim
58	95	Scale in Chip Interconnect requires Network Technology	claim
59	94	Reliability Support for On-Chip Memories Using Networks-on-Chip	claim
60	94	Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects	claim
61	92	Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy	claim
62	86	Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction	claim
63	84	Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation	claim
64	79	Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles	claim
65	77	Iterative-Constructive Standard Cell Placer for High Speed and Low Power	claim

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