Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in stronginversion. This presents new challenges in design optimization-particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
• Keywords: Current Drivability, Transistors, TVLSI 2008, Ultra-low Power Consumption