Static Program Partitioning for Embedded Processors

Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is required to partition and arrange the code such that appropriate fragments are loaded into the memory at appropriate times. We explore automatic partitioning by defining an optimality criterion and provide a lazy algorithm which tries to combine procedures which should be loaded together. The procedures which do not fit into local memory are further partitioned. The lazy nature of the algorithm facilitates using multiple heuristics to identify good partitions. Our partitioner can be used to provide the much needed relief to a programmer and could be an important tool in the design space exploration of embedded processor architectures to study the possibility of replacing expensive cache memory by relatively inexpensive and larger RAM.

• Type: Conference
• Year: 2006
• Where: CSREAESA
• Authors: Bageshri Sathe, Uday P. Khedker
• Keywords: Addressable Memory, CSREAESA 2006, CSREAESA 2007, Local Memory, On-chip Local Memory