Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage

In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, subthreshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and nonGaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G). Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Algorithm, Design, Performance, Reliability Keywords Statistical analysis, junction tunneling leakage, Gaussian and non-Gaussian parameter distributions

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Tao Li, Zhiping Yu
• Keywords: DAC 2007, Design Automation, Full-chip Leakage Power, Junction Tunneling Leakage, State-dependent Total Leakage