A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems

Synapses are a critical element of biologically-realistic, spike-based neural computation, serving the role of communication, computation, and modification. Many different circuit implementations of synapse function exist with different computational goals in mind. In this paper we describe a new CMOS synapse design that separately controls quiescent leak current, synaptic gain, and time-constant of decay. This circuit implements part of a commonly-used kinetic model of synaptic conductance. We show a theoretical analysis and experimental data for proto

• Type: Conference
• Year: 2003
• Where: NIPS
• Authors: Rock Z. Shi, Timothy K. Horiuchi
• Keywords: Commonly-used Kinetic Model, NIPS 2003, NIPS 2007, Spike-based Neural Computation, SYNAPSE