Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning

Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results s...

• Type: Conference
• Year: 2007
• Where: DSN
• Authors: Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani
• Keywords: Computer Networks, DSN 2007, Superscalar Processors, Timing Errors, Worst Case