ISQED
2007
IEEE
14 years 6 months ago
2007
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
DSN
2007
IEEE
14 years 6 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
DATE
2009
IEEE
14 years 7 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...