Survey and Evaluation of Low-Power Full-Adder Cells

In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments that compare the surveyed full-adder cells. The experiments simulate all combinations of input transitions and consequently determine the delay and power consumption for the various full-adder cells. Moreover, the simulation results highlight the weaknesses and the strengths of the various full-adder cell designs.

• Type: Conference
• Year: 2004
• Where: CSREAESA
• Authors: Ahmed Sayed, Hussain Al-Asaad
• Keywords: CSREAESA 2004, CSREAESA 2007, Full-adder Cell, Low-power Full-adder Cells, Various Full-adder Cell