Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems

In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation backplane. Distributed conservative eventdriven scheduling is used in combination with an efficient deadlock-free mechanism for handling synchronous feedback circuits. Simulation concurrency can be further increased by utilizing circuit pipeline. The resulting parallel simulation backplane is capable of concurrently simulating systems at circuit, switch, gate, RTL and behavioral levels. We implemented this parallel mixed-mode simulator on both the iPSC/860 message-passing machine and the DASH shared-memory multiprocessor. Experimental results are presented.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Antonio R. W. Todesco, Teresa H. Y. Meng
• Keywords: Computer Architecture, DAC 1996, Parallel Simulation Backplane, Simulation Backplane, Software Simulation Backplane