The Synergy of Multithreading and Access/Execute Decoupling

This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while decoupling features an excellent memory latency hiding efficiency, multithreading supplies the in-order issue stage with enough ILP to hide the functional unit latencies. Its partitioned layout, together with its in-order issue policy makes it potentially less complex, in terms of critical path delays, than a centralized out-of-order design, to support future growths in issue-width and clock speed. The simulations show that by adding decoupling to a multithreaded architecture, its miss latency tolerance is sharply increased and in addition, it needs fewer threads to achieve maximum throughput, especially for a large miss latency. Fewer threads result in a hardware complexity reduction and lower demands on the memory system, which becomes a critical resource for larg...

• Type: Conference
• Year: 1999
• Where: HPCA
• Authors: Joan-Manuel Parcerisa, Antonio González
• Keywords: Distributed And Parallel Computing, Fewer Threads, HPCA 1999, Latency Hiding Efficiency, Miss Latency