Sciweavers

HPCA
1999
IEEE
13 years 11 months ago
Instruction Recycling on a Multiple-Path Processor
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
Steven Wallace, Dean M. Tullsen, Brad Calder
HPCA
1999
IEEE
13 years 11 months ago
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor
This paper proposes and evaluates new synchronization schemes for a simultaneous multithreaded processor. We present a scalable mechanism that permits threads to cheaply synchroni...
Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henr...
HPCA
1999
IEEE
13 years 11 months ago
Permutation Development Data Layout (PDDL)
Declustered data organizations in disk arrays (RAIDs) achieve less-intrusive reconstruction of data after a disk failure. We present PDDL, a new data layout for declustered disk a...
Thomas J. E. Schwarz, Jesse Steinberg, Walter A. B...
HPCA
1999
IEEE
13 years 11 months ago
A Study of Control Independence in Superscalar Processors
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
Eric Rotenberg, Quinn Jacobson, James E. Smith
HPCA
1999
IEEE
13 years 11 months ago
Improving CC-NUMA Performance Using Instruction-Based Prediction
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
Stefanos Kaxiras, James R. Goodman
HPCA
1999
IEEE
13 years 11 months ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
HPCA
1999
IEEE
13 years 11 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
HPCA
1999
IEEE
13 years 11 months ago
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory
Processor speeds are increasing rapidly, and memory speeds are not keeping up. Streaming computations (such as multi-media or scientific applications) are among those whose perfor...
Sung I. Hong, Sally A. McKee, Maximo H. Salinas, R...
HPCA
1999
IEEE
13 years 11 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...