Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions

We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex RTL modules, such as FFTs and filters, as building blocks for the RTL circuit, in addition to simple RTL modules such as adders and multipliers. Unlike past techniques in the area, we also customize the complex RTL modules to match the environment in which they find themselves. We present a fast and efficient algorithm for mapping multiple behaviors onto the same RTL module during the course of synthesis, thus allowing our synthesis system to explore previously unexplored regions of the design space. These techniques are at the core of an iterative improvement based approach which can accept temporary degradation in solution quality in its quest for a globally optimal solution. The moves in our iterative improvement procedure explore optimizations along different dimensions such as functional unit selecti...

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Ganesh Lakshminarayana, Niraj K. Jha
• Keywords: Complex Rtl Modules, Computer Architecture, DAC 1998, Rtl Modules, Simple Rtl Modules