A Synthesizable IP Core for DVB-S2 LDPC Code Decoding

The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVBS2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255MBit/s for base station applications. In this paper we will show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0.13µm CMOS technology.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Frank Kienle, Torben Brack, Norbert Wehn
• Keywords: DATE 2005, Features Low-density Parity-check, Hardware, IP LDPC Decoder, Synthesizable Ip Block