System chip test: how will it impact your design?

A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challenges that come with testing deeply embedded reusable cores supplied by diverse providers, who often use different hardware description levels and mixed technologies. The paper describes a general test access architecture for embedded cores, and covers the current standardization efforts in this domain. In addition, we give an overview of the emerging EDA developments in SOC test, and illustrate the current industrial practices by means of two case studies.

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Yervant Zorian, Erik Jan Marinissen
• Keywords: Current Standardization Efforts, DAC 2000, Design Automation, Embedded Cores, Test Access Architecture