A System for Evaluating On-Line Testability at the RT-level

This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an exploration of different testable architectures before committing to the final design. Circuits are modeled as Finite State Machines, and a set of transformations can be defined inside the system to account for different on-line test strategies. Preliminary experiments show that the information made available by the evaluation system can be used to drive the testable design process towards a better trade-off point.

• Type: Conference
• Year: 1998
• Where: DFT
• Authors: Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti
• Keywords: DFT 1998, On-line Testable Circuit, Testable, Testable Design Process, VLSI