Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures

Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on the same architecture. This paper investigates systolic mapping techniques for mapping biosignal processing algorithms to CGRA architectures. A novel methodology using synchronous data flow (SDF) graphs and control and data flow (CDF) graphs for mapping is presented. Mapping signal processing algorithms in this manner is shown to give up to a 88% reduction in memory accesses and significant savings in fetch and decode operations while providing high throughput.

• Type: Conference
• Year: 2010
• Where: ARC
• Authors: Kunjan Patel, Chris J. Bleakley
• Keywords: ARC 2010, Biosignal Processing Algorithms, Hardware, Processing Algorithms, Systolic Mapping Techniques