A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems

A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology, it does not affect the design of the other layers, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the non-temporal correlation algorithm suffers from 30% performance loss.

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
• Keywords: Algorithm, FPL 2007, Hardware, Port Combination, Port Combination Algorithm