A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits

A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the sets of undetectable values of the trapped charge on the floating gate transistor. It covers all potential gate charges of an FGD at one or more transistors and allows the application of conventional circuit simulators for simulating DC, AC and transient test. Based on this fault simulation, a test design methodology is presented that can determine all test sets that detect all FGDs for all possible values of gate charge.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Michael Pronath, Helmut E. Graeb, Kurt Antreich
• Keywords: DATE 2002, Direct Fault Simulation, Fault Simulation, Gate Charge, Hardware