Test generation for designs with multiple clocks

To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize multiple clocks in the design effectively and efficiently in order to dramatically reduce test pattern count without sacrificing fault coverage or causing clock skew problem. This is achieved by pulsing multiple non-interactive clocks simultaneously and applying a clock concatenation technique. Experimental results on several industrial circuits show significant test pattern count reduction by using the proposed test generation procedures. Categories and Subject Descriptors B.8.1 Reliability, Testing, and Fault-Tolerance General Terms Algorithms, Design Keywords ATPG, Clock Domain, Scan Design

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Xijiang Lin, Rob Thompson
• Keywords: Clock, Computer Architecture, DAC 2003, Test Generation Procedures, Test Pattern Count