Test Generation for Ground Bounce in Internal Logic Circuitry

Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

• Type: Conference
• Year: 1999
• Where: VTS
• Authors: Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
• Keywords: Excessive Ground Bounce, Ground Bounce, Hardware, Internal Circuitry, VTS 1999