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VTS
1999
IEEE
68views Hardware» more  VTS 1999»
14 years 4 months ago
A Test Point Insertion Algorithm for Mixed-Signal Circuits
This paper presents an algorithm based on testability measurement for test point insertion of mixed-signal circuits. Two transfer function models compatible with analog models are...
Jinyan Zhang, Sam D. Huynh, Mani Soma
VTS
1999
IEEE
66views Hardware» more  VTS 1999»
14 years 4 months ago
A New Bare Die Test Methodology
1 While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that...
Zao Yang, K.-T. Cheng, K. L. Tai
VTS
1999
IEEE
88views Hardware» more  VTS 1999»
14 years 4 months ago
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venk...
VTS
1999
IEEE
83views Hardware» more  VTS 1999»
14 years 4 months ago
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
Philip P. Shirvani, Edward J. McCluskey
VTS
1999
IEEE
114views Hardware» more  VTS 1999»
14 years 4 months ago
Partial Scan Using Multi-Hop State Reachability Analysis
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
Sameer Sharma, Michael S. Hsiao
VTS
1999
IEEE
76views Hardware» more  VTS 1999»
14 years 4 months ago
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
Maurizio Rebaudengo, Matteo Sonza Reorda
VTS
1999
IEEE
81views Hardware» more  VTS 1999»
14 years 4 months ago
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
Debashis Nayak, D. M. H. Walker
VTS
1999
IEEE
125views Hardware» more  VTS 1999»
14 years 4 months ago
Error Detecting Refreshment for Embedded DRAMs
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test c...
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexa...
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
14 years 4 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
VTS
1999
IEEE
108views Hardware» more  VTS 1999»
14 years 4 months ago
Adaptive Techniques for Improving Delay Fault Diagnosis
This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failur...
Jayabrata Ghosh-Dastidar, Nur A. Touba