Thermal aware cell-based full-chip electromigration reliability analysis

A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermalaware reliability analysis for true reliability aware design. Categories and Subject Descriptors B.7.0 [I...

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Syed M. Alam, Donald E. Troxel, Carl V. Thompson
• Keywords: Full-chip Reliability, GLVLSI 2005, Reliability Analysis, Reliability Aware Design, VLSI