Thermal optimization in multi-granularity multi-core floorplanning

—Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of these factors at an early stage. Toward this goal, this work presents the first adaptive multi-granularity multi-core microarchitecture-level floorplanner that simultaneously optimizes temperature and performance, and considers memory bus length. We include simultaneous optimization at both the module-level and the core/cache-bank level. Related experiments show that our methodology is effective for optimizing multi-core architectures.1

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
• Keywords: ASPDAC 2009, Careful Balance, Memory Bus Length, Multi-core Microarchitecture-level floorplanner