A three-port adiabatic register file suitable for embedded applications

Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs, and any circuit of even moderate complexity requires some form of ram. This paper presents a register file implemented entirely with adiabatic logic, and fabricated

• Type: Conference
• Year: 1998
• Where: ISLPED
• Authors: Stephan Avery, Marwan A. Jabri
• Keywords: Adiabatic Logic, Adiabatic Memory Designs, Hardware, ISLPED 1998, Slower Clock Rates