Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores

—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multiprocessing, a popular approach for performance enhancement, opens up the opportunity for concurrent execution. However due to contention for any shared memory by different processing cores, memory access behavior becomes more unpredictable, and hence harder to analyze. In this paper, we develop a timing analysis method for concurrent software running on multi-cores with a shared instruction cache. Communication across tasks is by message passing where the message mailboxes are accessed via interrupt service routines. We do not handle data cache, shared memory synchronization and code sharing across tasks. Our method progressively improves the lifetime estimates of tasks that execute concurrently on multiple cores, in order to estimate potential conflicts in the shared cache. Possible conflicts arising from ove...

• Type: Conference
• Year: 2009
• Where: RTSS
• Authors: Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Abhik Roychoudhury
• Keywords: Applied Computing, Memory Accesses, RTSS 2009, Shared Memory, Timing Analysis