Timing-driven N-way decomposition

Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techniques to reduce the depth of the netlist due to the affordable computational cost. We present a novel n-way decomposition technique that improves bi-decomposition. The problem of decomposition is formulated as a Boolean relation which captures a larger set of possible solutions compared to bi-decomposition. The solution obtained from the Boolean relation improves the delay with near-zero cost in area. As it is shown on the experimental results, a considerable improvement is achieved on large netlists and even larger depending on which technology mapper is used. Categories and Subject Descriptors: B.6.3 [Hardware]: Logic Design - Design Aids; J.6 [Computer Applications]: Computeraided engineering Terms: Algorithms, Design.

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: David Bañeres, Jordi Cortadella, Michael Kishinevsky
• Keywords: Affordable Computational Cost, Boolean Relation, Decomposition, GLVLSI 2009, VLSI