Token Coherence: Decoupling Performance and Correctness

Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence in these systems is difficult, because traditional approaches either add indirection for common cache-to-cache misses (directory protocols) or require a totally-ordered interconnect (traditional snooping protocols). Unfortunately, totally-ordered interconnects are difficult to implement in glueless designs. An ideal coherence protocol would avoid indirections and interconnect ordering; however, such an approach introduces numerous protocol races that are difficult to resolve. We propose a new coherence framework to enable such protocols by separating performance from correctness. A performance protocol can optimize for the common case (i.e., absence of races) and rely on the underlying correctness substrate to resolve races, provide safety, and prevent starvation. We call the combination Token Coherence, si...

• Type: Conference
• Year: 2003
• Where: ISCA
• Authors: Milo M. K. Martin, Mark D. Hill, David A. Wood
• Keywords: Directory Protocols, Hardware, ISCA 2003, Low-latency Cache Coherence, Token Coherence