Tools and devices supporting the pseudo-exhaustive test

: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, instead of path-sensitizing. The developed cells segment the entire circuits into exhaustively testable parts, and the presented algorithms place these cells, under the objective to minimize the hardware overhead. The approach is completely compatible with the usual LSSDrules. The analysis of the well-known benchmark circuits shows only little additional hardware costs.

• Type: Conference
• Year: 1990
• Where: EURODAC
• Authors: Sybille Hellebrand, Hans-Joachim Wunderlich
• Keywords: EURODAC 1990, Paper Logical Cells, Real Hardware Segmentation, Testable Circuits, VHDL