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EURODAC
1990
IEEE
73views VHDL» more  EURODAC 1990»
14 years 3 months ago
A new method for the state reduction of incompletely specified finite sequential machines
Maria J. Avedillo, José M. Quintana, Jos&ea...
EURODAC
1990
IEEE
72views VHDL» more  EURODAC 1990»
14 years 3 months ago
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler
J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man
EURODAC
1990
IEEE
92views VHDL» more  EURODAC 1990»
14 years 3 months ago
Accelerated test pattern generation by cone-oriented circuit partitioning
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
Torsten Grüning, Udo Mahlstedt, Wilfried Daeh...
EURODAC
1990
IEEE
74views VHDL» more  EURODAC 1990»
14 years 3 months ago
Matching system and component behaviour in MIMOLA synthesis tools
This paper discusses the selection of available components during high-level synthesis. We stress the importance of describing the behaviour of available components in some langua...
Peter Marwedel
EURODAC
1990
IEEE
102views VHDL» more  EURODAC 1990»
14 years 3 months ago
Tools and devices supporting the pseudo-exhaustive test
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
Sybille Hellebrand, Hans-Joachim Wunderlich