Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems

Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while following the synchronous design paradigm. In a latency-insensitive system (LIS), each core is encapsulated within a shell, which is a synthesized interface module that dynamically controls its operation. At each clock period, if new data have not arrived on an input channel or if a stalling request has arrived on an output channel, the shell stalls the core and buffers other incoming valid data for future processing. The combination of finite buffers and backpressure from stalling can cause throughput degradation. Previous works addressed this problem by increasing buffer space to reduce the backpressure requests or inserting extra buffering to balance the channel latency around a LIS. We explore the theoretical complexity of these approaches and propose a heuristic algorithm for efficient queue sizing (QS). We e...

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Rebecca L. Collins, Luca P. Carloni
• Keywords: Heuristic Algorithm, Intercore Communication Channels, Synchronous Design Paradigm, TCAD 2008