Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in the physical design stage. It can be shown that proper queue sizing can reduce or even completely avoid the performance loss due to imbalanced relay stations insertion in reconvergent paths. Moreover, the problem of queue sizing and placement of the additional buffers for maximum performance is formulated and studied to properly allocate available chip areas in the layout to communication channels. An algorithm based on mixed integer linear programming is proposed. Experimental results show that queue sizing is effective in improving the performance of latency insensitive systems even under tight area constraints. Moreover, the proposed algorithm is sufficiently efficient in obtaining the optimal solution for systems of practical sizes.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Ruibing Lu, Cheng-Kok Koh
• Keywords: Channel Buffer Queue, Hardware, ICCAD 2003, Latency Insensitive Systems, Sizing