Toward a systematic-variation aware timing methodology

Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance. Since many factors contribute to the variability of gate length, recent studies have modeled the variability using Gaussian distributions. In reality, the through-pitch and through-focus variations of gate length are systematic. In this paper, we propose a timing methodology which takes these systematic variations into account and we show that it can reduce the timing uncertainty by up to 40%. Categories and Subject Descriptors B.7.2 [Design Aids]: Layout General Terms Algorithms, Design, Performance Keywords Layout, Lithography, OPC, ACLV, Manufacturability

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Puneet Gupta, Fook-Luen Heng
• Keywords: Circuit Performance, DAC 2004, Design Automation, Gate Length, Gate Length Variation