Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes

Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which were used to design a novel low-complexity programmable decoder architecture with throughput in the range of 1 Gbit/s at moderate system clock frequencies. The synthesis results indicate that the decoder requires relatively small areas, even when high levels of parallelism are used.

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Emil Matús, Marcos B. S. Tavares, Marcel Bimberg, Gerhard Fettweis
• Keywords: ISCAS 2007, LDPC Convolutional Codes, Programmable Decoder Architecture, Signal Processing Scheme