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ISCAS 2007 International Symposium on Circuits and Systems

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ISCAS
2007
IEEE

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FIR Filter Approximation by IIR Filters Based on Discrete-Time Vector Fitting

14 years 5 months ago

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— We present a novel way of approximating FIR ﬁlters by IIR structures through generalizing the vector ﬁtting (VF) algorithm, popularly used in continuous-time frequency-doma...

Ngai Wong, Chi-Un Lei

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Id	Views	Title	Status

1	371	FIR Filter Approximation by IIR Filters Based on Discrete-Time Vector Fitting	claim
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3	241	Image Denoising using Shiftable Directional Pyramid and Scale Mixtures of Complex Gaussians	claim
4	222	A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters	claim
5	208	Adaptive Lagrange Multiplier Selection for Intra-Frame Video Coding	claim
6	207	Low-delay View Random Access for Multi-view Video Coding	claim
7	202	A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform	claim
8	193	3D Object-based Scalable Wavelet Video Coding with Boundary Effect Suppression	claim
9	189	Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications	claim
10	181	Image Compression using 2D Dual-tree Discrete Wavelet Transform (DDWT)	claim
11	180	Characterization of a Fault-tolerant NoC Router	claim
12	179	Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method	claim
13	179	A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications	claim
14	178	On the Joint Compensation of IQ Imbalances and Phase Noise in MIMO-OFDM Systems	claim
15	176	SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier	claim
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17	173	Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM	claim
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20	171	Using H.264/AVC-based Scalable Video Coding (SVC) for Real Time Streaming in Wireless IP Networks	claim
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32	149	Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals	claim
33	149	Low-Power Circuits for Brain-Machine Interfaces	claim
34	149	Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition	claim
35	149	New Light-Weight Crypto Algorithms for RFID	claim
36	149	Address-Event Video Streaming over Wireless Sensor Networks	claim
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46	142	Visualization of SystemC Designs	claim
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48	142	Effect of Word-length Precision on the Performance of MIMO Systems	claim
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54	139	A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method	claim
55	139	Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs	claim
56	138	A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits	claim
57	138	Adaptive Pinning Synchronization of A General Complex Dynamical Network	claim
58	138	A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement	claim
59	138	Highly Linear Bipolar Transconductor For Broadband High-Frequency Applications with Improved Input Voltage Swing	claim
60	137	Implantable MEMS Accelerometer Microphone for Cochlear Prosthesis	claim
61	137	Satellite Navigation: New Signals, New Challenges	claim
62	136	An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings	claim
63	136	A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless Receivers	claim
64	136	Chopper Modulation Improves OTA Information Transmission	claim
65	136	Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters	claim
66	136	Flexible Low Power Probability Density Estimation Unit For Speech Recognition	claim
67	135	Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology	claim
68	135	Application-Specific Instruction Generation for SOC Processors	claim
69	135	Diophantine Frequency Synthesis The Mathematical Principles	claim
70	134	Macroblock-Based Adaptive In-Scale Prediction for Scalable Video Coding	claim
71	134	Florida Wireless Implantable Recording Electrodes (FWIRE) for Brain Machine Interfaces	claim
72	134	4.7pJ/pulse 7th Derivative Gaussian Pulse Generator for Impulse Radio UWB	claim
73	133	GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis	claim
74	133	Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture	claim
75	133	Volterra Analysis Using Chebyshev Series	claim
76	132	High Read Stability and Low Leakage Cache Memory Cell	claim
77	132	Public-Key Cryptography on the Top of a Needle	claim
78	132	On-Line Histogram Equalization for Flash ADC	claim
79	132	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions	claim
80	131	2-MITE Product-of-Power-Law Networks	claim
81	130	Classes of stochastically switched (blinking) systems	claim
82	130	Improving Video Coding at Scene Cuts using Attention based Adaptive Bit Allocation	claim
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87	128	Collaborative Routing Architecture for FPGA	claim
88	128	Analysis of Second-Order Modes of Linear Continuous-Time Systems under Positive-Real Transformations	claim
89	128	Synchronization of the Time-Varying Discrete Biological Networks	claim
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101	123	Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs	claim
102	123	Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors	claim
103	122	Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks	claim
104	122	Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive Control	claim
105	122	Fast sensory motor control based on event-based hybrid neuromorphic-procedural system	claim
106	122	Eigenvector Algorithms for Blind Deconvolution of MIMO-IIR Systems	claim
107	122	Living and Dealing with RF Impairments in Communication Transceivers	claim
108	121	Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design	claim
109	121	Precise RSSI with High Process Variation Tolerance	claim
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111	120	CREMA: A Parallel Hardware Raytracing Machine	claim
112	120	Clock Gating and Negative Edge Triggering for Energy Recovery Clock	claim
113	120	DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure	claim
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119	117	On the Impact of I/Q Imbalance in Multi-Carrier Systems for Different Channel Scenarios	claim
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123	114	A Spike-Based Saccadic Recognition System	claim
124	114	Low-Power Digitally Controlled CMOS Source Follower Variable Attenuator	claim
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126	114	A 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interface	claim
127	114	On the Suitability of Discrete-Time Receivers for Software-Defined Radio	claim
128	114	On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs	claim
129	114	The RunBot Architecture for Adaptive, Fast, Dynamic Walking	claim
130	113	A Circuit-Based Noise Parameter Extraction Technique for MOSFETs	claim
131	113	A General Noncoherent Chaos-Shift-Keying Communication System and its Performance Analysis	claim
132	113	Design Considerations for Future RF Circuits	claim
133	113	Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators	claim
134	113	A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio	claim
135	112	Motion Detection Circuits for a Time-To-Travel Algorithm	claim
136	112	A New Statistical Approach for Glitch Estimation in Combinational Circuits	claim
137	112	Motion Mapping for MPEG-2 to H.264/AVC Transcoding	claim
138	111	Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform	claim
139	111	Using FPGA for visuo-motor control with a silicon retina and a humanoid robot	claim
140	111	Boundaries Between Fast-and Slow-Scale Bifurcations in Parallel-Connected Buck Converters	claim
141	110	On the degree of MIMO systems	claim
142	110	A Novel Active Decoupling Capacitor Design in 90nm CMOS	claim
143	109	Optimization of Gabor Features for Text-Independent Speaker Identification	claim
144	109	Macroblock-level Reduced Resolution Video Coding Allowing Adaptive DCT Coefficients Selection	claim
145	109	Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding	claim
146	109	A Method to Reduce the Effect of the Switching Noise in Analog-Mixed Circuits	claim
147	108	Optimal Synthesis of MITE Translinear Loops	claim
148	108	On the Hardware Reduction of z-Datapath of Vectoring CORDIC	claim
149	108	A Low Power Digital Baseband for Wireless Endoscope Capsule	claim
150	108	Linear Prediction Based Semi-Blind Channel Estimation for MIMO-OFDM System	claim
151	108	Mixed-Order Sturdy MASH Delta-Sigma Modulator	claim
152	107	Architecture Level Power-Performance Tradeoffs for Pipelined Designs	claim
153	107	Low power variable block size motion estimation using pixel truncation	claim
154	106	Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design	claim
155	106	Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation	claim
156	106	Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics	claim
157	105	Parallel current-steering D/A Converters for Flexibility and Smartness	claim
158	105	Stability Analysis of RED Gateway with Multiple TCP Reno Connections	claim
159	105	A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator	claim
160	105	A Low Power Sinc3 Filter for Sigma-Delta Modulators	claim
161	105	A Parallel, Multi-Resolution Sensing Technique for Multiple Antenna Cognitive Radios	claim
162	104	A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback	claim
163	104	Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit	claim
164	104	Evaluation of Algorithms for Low Energy Mapping onto NoCs	claim
165	104	Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors	claim
166	104	Noncoherent Correlation-Based Communication Systems Choosing Different Chaotic Maps	claim
167	103	Hopf-Type Intermediate-Scale Bifurcation in Single-Stage Power-Factor-Correction Power Supplies	claim
168	103	Multi-Vth Level Conversion Circuits for Multi-VDD Systems	claim
169	103	A Low-cost and High-performance SoC Design for OMA DRM2 Applications	claim
170	103	Sliding-Window Digital Fountain Codes for Streaming of Multimedia Contents	claim
171	101	Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing	claim
172	101	Automated HDL Generation: Comparative Evaluation	claim
173	101	Flexible and Cost Effective Transport Stream Processor for DTV	claim
174	100	Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency	claim
175	99	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints	claim
176	99	FRM-Based FIR Filters with Minimum Coefficient Sensitivities	claim
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178	98	Vertically-Integrated Three-Dimensional SOI Photodetectors	claim
179	97	Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency	claim
180	97	Modeling the Telephone Call Network	claim
181	96	Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers	claim
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184	96	Novel High-Speed Redundant Binary to Binary converter using Prefix Networks	claim
185	96	Modeling and Synthesis of Hardware-Software Morphing	claim
186	96	Leakage-based On-Chip Thermal Sensor for CMOS Technology	claim
187	96	Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates	claim
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191	95	A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers	claim
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194	94	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM	claim
195	94	Run-Time Programming of Analog Circuits Using Floating-Gate Transistors	claim
196	94	A Simplified Structure for FIR Filters with an Adjustable Fractional Delay	claim
197	93	High Speed Sphere Decoding Based on Vertically Incremental Computation	claim
198	93	Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform	claim
199	93	VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding	claim
200	93	Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring Systems	claim
201	93	Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator	claim
202	92	A Study on Impact of Leakage Current on Dynamic Power	claim
203	92	Multifunctional RF Transmitters for Next Generation Wireless Transceivers	claim
204	92	Amperometric Readout and Electrode Array Chip for Bioelectrochemical Sensors	claim
205	92	Companding Baseband Switched Capacitor Filters and ADCs for WLAN Applications	claim
206	92	Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients	claim
207	91	A New Handheld Biochip-based Microsystem	claim
208	91	Fundamental Performance Limits in Lossy Polyphase Systems: Apparent Power and Optimal Compensation	claim
209	91	Power Harvesting With PZT Ceramics	claim
210	90	Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse Response	claim
211	90	Leakage-Aware Design of Nanometer SoC	claim
212	89	Tonality Index of Sigma-Delta Modulators : A Psychoacoustics Model Based Approach	claim
213	89	Switching Phase States of Chaotic Circuits Coupled by Time-Varying Resistor	claim
214	89	Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic Approach	claim
215	88	Effective Search with Hopping Chaos for Hopfield Neural Networks Solving QAP	claim
216	86	Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier	claim
217	86	UEP for Progressive Image Transmission with GA-based Optimization	claim
218	85	Silicon neurons that burst when primed	claim
219	84	Piezo-powered floating gate injector for self-powered fatigue monitoring in biomechanical implants	claim
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221	84	High Speed 1-bit Bypass Adder Design for Low Precision Additions	claim
222	84	System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint	claim
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235	76	In Vitro Epileptic Seizure Prediction Microsystem	claim
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