Towards Optimal Multi-level Tiling for Stencil Computations

Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many tiling and parallelization strategies are applicable to a given stencil computation. The best strategy depends not only on the combination of the two techniques, but also on many parameters: tile and loop sizes in each dimension; computation-communication balance of the code; processor architecture; message startup costs; etc. The best choices can only be determined through design-space exploration, which is extremely tedious and error prone to do via exhaustive experimentation. We characterize the space of multi-level tilings and parallelizations for 2D/3D GaussSiedel stencil computation. A systematic exploration of a part of this space enabled us to derive a design which is up to a factor of two faster than the standard implementation.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Lakshminarayanan Renganarayanan, Manjukumar Harthikote-Matha, Rinku Dewri, Sanjay V. Rajopadhye
• Keywords: Distributed And Parallel Computing, GaussSiedel Stencil Computation, IPPS 2007, Parallelization, Stencil Computation