Training IP Creators and Integrators

Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time to market which results in increased pro ts. Alliances of companies have been formed to support an open market for IP and standards are being devised to ensure the quality of this IP. Also, a web-based network has been set up to facilitate the matching of providers and consumers. However, a signi cant problem still needs be addressed: namely, the widespread training of IP creators and integrators. In recent years, universities have been o ering courses which involve logic synthesis and simulation using VHDL or Verilog along with veri cation using FPGAs. Now that standards for IP reuse are being developed, these courses need to require students to develop and integrate IP blocks which are compliant with the desired quality level. In this paper, we describe the procedure that we have begun using at the Universi...

• Type: Conference
• Year: 1999
• Where: MSE
• Authors: Donald W. Bouldin, Senthil Natarajan, Benjamin A. Levine, Chandra Tan, Danny Newport
• Keywords: Hardware, IP Blocks, IP Creators, MSE 1999, Property Ip Blocks