Transaction-Aware Network-on-Chip Resource Reservation

Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. However, these benefits come at the price of router latency due to run-time multihop data buffering and resource arbitration, which account for the majority of on-chip transaction latency. In this work, we address the latency issue of on-chip network design and propose dynamic in-network resource reservation techniques that are guided by highta transaction information. This idea is motivated by the need to preserve existing abstraction and general-purpose network performance while optimizing for latency-critical events. Experiments with multithreaded benchmarks demonstrate that the proposed techniques reduce on-chip data access latency and demonstrate the importance of considering transaction-level information in network design.

• Type: Journal
• Year: 2008
• Where: CAL
• Authors: Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, Yihe Sun
• Keywords: CAL 2008, Facto On-chip Data, On-chip Data, On-chip Network Design, Software Engineering