Transformation and synthesis of FSMs for low-power gated-clock implementation

We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transformation for general incompletely specied Mealy-type machines that makes them suitable for gated clock implementation. The transformation is probabilistic-driven, and leads to the synthesis of an optimized combinational logic block that stops the clock with high probability. A prototype tool has been implemented and its performance, although strongly in uenced by the initial structure of the nite state machine, shows that sizable power reductions can be obtained with our technique.

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Luca Benini, Giovanni De Micheli
• Keywords: Gated Clock, Hardware, ISLPED 1995, Nite State Machine, Optimized Combinational Logic