Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and domino CMOS. Circuits designed in these non-dual ratioed logic families can be highly irregular with complex geometry sharing and non-trivial routing. Traditional digital cell layout synthesis tools derived from the row-based “functional cell” style break down when confronted with such circuit topologies. These cells require a full-custom 2dimensional layout style which currently requires skilled manual design. In this work we define the synthesis of complex 2-dimensional digital cells as a new problem which we call transistor-level micro-placement and routing. To address this problem we develop a complete end-to-end methodology which is implemented in a prototype tool named TEMPO. Our primary focus in this work is the micro-placement problem. We explore techniques for the modeling and dynamic optimization ...

• Type: Conference
• Year: 1999
• Where: ISPD
• Authors: Michael A. Riepe, Karem A. Sakallah
• Keywords: Cascode Voltage Switch Logic, Geometry Sharing, Hardware, ISPD 1999, Logic Families